Unix Socket Programming
I implemented a library management network using C++ in a Linux environment. Five servers were created, "Client", "Main", "Science", "History" and "Literature". The Client and Main servers communicated over TCP for a reliable connection, while the Main server communicated with the three backend servers over UDP. To start the program, ports for the Client and Main servers need to be opened first. The Client is prompted to enter a username and password. The program parses through the input .txt files provided to determine if the username/password combination is in the system. If it is not, the user will be prompted to try again. Otherwise, the user gains access to the library system. If the admin username/password is entered, more access is given, which is described later. The user is next prompted to enter a book code for either the Science, History, or Literature department. The request is send to the Main server. The Main server sends a request to the appropriate backend server. The backend server checks the book code against the .txt files, then sends status (avaliable or not avaliable) back to the Main server. The Main server relays this information to the Client server. If the Client is accessing the system as an Admin, the number of books avaliable under that book code will also appear. The number of books avaliable under the book code will decrease every time a client sends a request to check the book out.
FPGA Programming
I became familiar with Modelsim and Xilinx Vivado while learning how to program the Nexys 7 FPGA. For one of my projects, I wrote VHDL code for a divider, cache, CAM and LRU stack to implement a divider with cache. I also wrote a testbench to verify functionality of my code using Modelsim waveforms. Once the design was tested, I used Vivado to synthesize the project and created a bitstream to program the FPGA. Using UART, I sent a 4 bit hex number to the FPGA where the first 2 bits represented the dividend and the last 2 bits represented the divisor. I stepped through division using a button on the FPGA until the result appeared on the FPGA screen, where the first 2 bits represented the quotient and the last 2 bits represented the remainder.
Class D Amplifier
For my senior design project at SDSU, I worked with four other engineers to design a 10W Class D Amplifier with less than 1% THD. Click the link below for the system design.